Level shifters are frequently used for shifting the low and high levels of a digital signal output from one part of a system to different low and high levels required by another part of the same system.
One of the technical fields in which level shifters are required is the field of Liquid Crystal Displays (LCD). Level shifters must here transform the logic levels of the control signals of a timing controller providing for example a difference between low and high voltage level of less than 5 V into positive and negative drive signals of an appropriate level which depends on a particular LCD display and can reach several tens of volts. Present-generation LCDs using amorphous silicon gates (ASG), also called Gate-in-Panel (GIP) or Gate-On-Array (GOA) need drive voltages between about 20 V to 40 V for the high level and between about −5 V to −20 V for the low level resulting in a voltage difference from 25 V up to 60 V.
FIG. 1 shows simplified circuit and block diagram of an electronic device 1 according to the prior art. The electronic device comprises a control logic 2, two gate drivers 3 and 4 for driving the gates of transistors (MOSFETs) Q9 and Q10. In this example, transistors Q9 and Q10 are both PMOS transistors. Transistor Q9 is also referred to as the high-side transistor and transistor Q10 is also referred to as the low-side transistor. The source of transistor Q9 is coupled to a relatively high supply voltage level VGH (up to 40 V and more). The drain of transistor Q9 is coupled to the source of transistor Q10 at node VGHM. Node VGHM is the driving node which can be coupled to a capacitive load (not shown), as for example an LCD display. The drain of transistor Q10 is coupled to a resistor RE. The resistor RE serves to define a specific slope of the current through Q10 and is dimensioned in accordance with the requirements of the target application. The control logic 2 receives a signal GVOFF that varies between voltage levels of a low supply voltage domain (for example between 0 V and 5 V) and provides driving control signals DR9 and DR10 (comprising Q10ON, Q10OFF) to the driving stage 3 and 4. Driving stage 3 is also referred to as high-side driving stage and driving stage 4 is also referred to as low-side driving stage. Driving control signals DR9 and DR10 have the voltage levels of the low supply voltage domain. Driving Pin VGHM is supposed to drive a load with voltage levels up to 40 V or more, i.e. with voltage levels of the high supply voltage domain. The gate drivers 3 and 4 are coupled to the control gates of transistors Q9 and Q10. The gate control signals G9 and G10 have to be configured such that transistors Q9 and Q10 can be completely turned on and off. This creates various problems with respect to the timing and the voltage levels that are required from control signals G9 and G10.
FIG. 2 shows a simplified circuit diagram of a prior art circuit that is used for driving the gate of the transistor Q10. The channels of transistors Q9 and Q10 are coupled in series as shown in FIG. 1. High-side transistor Q9 is coupled between the driving node VGHM and the high supply voltage VGH. Low-side Q10 is coupled with its channel between node VGHM and node to which the resistor RE (not shown) can be coupled. The high-side gate driving stage for transistor Q9 is not shown as this gate driver is less critical. There is a low-side gate driver (corresponding to driving stage 4 in FIG. 1) that comprises transistors M0 to M5, an overstress protection diode D0 and a bias current source 12. Transistors M1, M2, M4 and M5 are PMOS transistors. Transistors M0 and M3 are NMOS transistors. The control gates of transistors M0 and M3 receive control signals Q10ON and Q10OFF, respectively. The control signals are provided by control stage 2 (as shown in FIG. 1). The sources of transistors M0 and M3 are coupled to ground. The drain of transistor M0 is coupled to the drain of transistor M2. The drain of transistor M3 is coupled to the drain of transistor M1. The gates of transistors M2 and M1 are coupled together and to one side of the bias current source 12 and the anode of Zener diode D0. The other side of bias current source 12 is coupled to ground. The Zener diode D0 is further coupled with its cathode to node VGHM. The source of transistor M2 is coupled to the drain of transistor M4, to the gate of transistor M5 and to the gate of transistor Q10. Accordingly, this node provides the control signal G10 for the gate of transistor Q10. The source of transistor M1 is coupled to the drain of transistor M5 and to the gate of transistor M4. The sources of transistors M4 and M5 are coupled to node VGHM. Transistors M4 and M5 are cross-coupled so as to ensure that the control signal G10 is always in a stable state. In response to signals Q10OFF and Q10ON, node G10 (i.e. control signal G10) is either pulled to the voltage level at node VGHM or to ground. If, for example Q10ON is high (greater than the threshold voltage level of M0) and Q10OFF is low (lower than the threshold voltage level of M3), node G10 is pulled to ground. Transistor Q10 is turned on provided that the voltage level at VGHM is high enough. If signal Q10ON is low (lower than the threshold voltage level of M0) and Q10OFF is high (higher than the threshold voltage level of M3), node G10 is pulled to VGHM. Transistor Q10 is then turned off. However, if node VGHM is discharged to ground level, this can cause shoot through current through transistors Q9 and Q10 and resistor RE at the beginning of a new pulse. This shoot through current is due to the fact that VGHM needs to exceed at least one threshold voltage level VT before the gate driving stage 4 can react and turn off transistor Q10.
This problem was addressed with capacitive bootstrap circuits which were configured to raise the gate voltage of Q10 faster than through the voltage at node VGHM. However, these prior art circuits also failed to completely prevent shoot through current. Furthermore, the capacitive bootstrap circuit requires a comparatively large capacitor that is also suitable for the voltage levels in the high voltage domain. The area consumed by this capacitor is too large, if the gate drive is integrated in an integrated semiconductor device. If the ON-resistance of the low-side transistor Q10 has to be reduced, the gate capacitance of transistor Q10 increases. The prior art gate driving stage 3 may then not be able to charge control gate of Q10 fast enough. In some prior art solutions, this is overcome by coupling one or more inverters between the output node of the gate driving stage 3 and the control gate of Q10. However, in this prior art configuration it becomes difficult to supply the inverters properly between ground and VGHM in order not to violate the maximum gate-source and drain-source voltage limits of transistor in the inverters or of Q10. These circuits still suffer from some shoot through current.
Furthermore, there are target applications for level shifters where the voltage level at node VGHM should not drop below a predefined voltage level. This requirement can not be met with the previously described level shifters and gate drivers.